Senior Formal Verification Engineer

Job Description

You are tasked with finding the Impossible Bug. You will use mathematical model checking to ensure the Janus Core intercepts every non-deterministic AI command. You will work directly with the RTL design team to fix logic leaks at the source.

Key Responsibilities include:

Model Checking: Deploy SAT/SMT solvers (like Z3) to verify arithmetic and logic properties.

Connectivity Verification: Prove that there is no data-leakage path that bypasses the Veto gate.

Security Auditing: Conduct Logic Locking verification to ensure the hardware safety rules are tamper-proof

Required Qualifications & Experience

Education: BSc/BEng in Electrical Engineering or Applied Mathematics.

Experience: 6–10 years in digital verification.

Skills: Proficiency in SystemVerilog/UVM and scripting (Python/TCL).

Mindset: A Breaker mentality—you must be obsessed with proving the design wrong until it is proven right.

Salary: Neg + Equity